74LVQ174_99 View Datasheet(PDF) - STMicroelectronics
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Description
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74LVQ174_99 Datasheet PDF : 10 Pages
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74LVQ174
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns)
Symb ol
Parameter
T est Con ditio n
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
Unit
tPLH Propagation Delay Time
tPHL CK to Q
2.7
3.3(*)
7.0 15.0
5.5 11.0
17.0 ns
12.0
tPHL Propagation Delay Time
CLR to Q
2.7
3.3(*)
8.5 16.0
7.0 12.0
18.0 ns
13.0
tw(L) CLR pulse Width, LOW
2.7
3.3(*)
1.0 7.0
1.0 5.5
10.0 ns
7.0
tw CK pulse Width, HIGH or
LOW, 2.7
3.3(*)
1.0 7.0
10.0 ns
1.0 5.5
7.0
tsL Setup Time D to CK HIGH
2.7
tsH or LOW
3.3(*)
-0.5 8.0
-0.4 6.5
10.0 ns
7.0
thL Hold Time D to CK HIGH
thH or LOW
2.7
3.3(*)
0.5 4.0
0.4 3.0
4.5
ns
3.0
tREM Recovery Time CLR to CK
2.7
3.3(*)
0.5 3.5
0.4 2.5
3.5
ns
2.5
fMAX Maximum Clock Frequency 2.7
3.3(*)
60 150
50
MHz
90 150
70
tOSLH Output to Output Skew
tOSHL Time (note 1, 2)
2.7
3.3(*)
0.5 1.0
0.5 1.0
1.5 ns
1.5
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the
same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tpHLn|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
Test Conditions
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
Unit
CIN Input Capacitance
3.3
5
pF
CPD Power Dissipation
3.3
fIN = 10 MHz
23
pF
Capacitance (note 1)
1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/6(per flipflop)
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