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74LVQ373M View Datasheet(PDF) - STMicroelectronics

Part Name74LVQ373M ST-Microelectronics
STMicroelectronics ST-Microelectronics
DescriptionOCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING
74LVQ373M Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
74LVQ373
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC Supply Voltage
-0.5 to +7
V
VI
DC Input Voltage
-0.5 to VCC + 0.5
V
VO DC Output Voltage
-0.5 to VCC + 0.5
V
IIK
DC Input Diode Current
± 20
mA
IOK DC Output Diode Current
± 20
mA
IO
DC Output Current
± 50
mA
ICC or IGND DC VCC or Ground Current
± 400
mA
Tstg Storage Temperature
-65 to +150
oC
TL
Lead Temperature (10 sec)
300
oC
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC Supply Voltage (note 1)
VI
Input Voltage
VO
Output Voltage
Top Operating Temperature:
tr, tf Input Rise and Fall Time (VCC = 3V) (note 2)
1) Truth Table guaranteed: 1.2V to 3.6V
2) VIN from 0.8V to 2V
Valu e
2 to 3.6
0 to VCC
0 to VCC
-40 to +85
0 to 10
Unit
V
V
V
oC
ns/V
3/10
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DESCRIPTION
The LVQ373 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.It is ideal for low power and low noise 3.3V applications.
These 8 bit D-Type latchs are controlled by a latch enable input (LE) and an output enable input (OE).
While the LE input is held at a high level, the Q outputs will follow the data input precisely.
When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state.
It has better speed performance at 3.3V than 5V LS-TTL family combined with the true CMOS low power consuption.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 6 ns (TYP.) at VCC = 3.3V
■ COMPATIBLEWITH TTL OUTPUTS
■ LOW POWER DISSIPATION:
   ICC =4 µA (MAX.) at TA = 25 °C
■ LOW NOISE: VOLP = 0.4V(TYP.) at VCC = 3.3V
■ 75Ω TRANSMISSIONLINE OUTPUT DRIVE CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 12 mA (MIN)
■ PCI BUS LEVELSGUARANTEED AT 24mA
■ BALANCEDPROPAGATIONDELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGERANGE:
   VCC (OPR)= 2V to 3.6V (1.2VData Retention)
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373
■ IMPROVED LATCH-UP IMMUNITY

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