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74LVQ373M データシートの表示(PDF) - STMicroelectronics

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74LVQ373M OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING ST-Microelectronics
STMicroelectronics ST-Microelectronics
74LVQ373M Datasheet PDF : 10 Pages
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®
74LVQ373
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUTS NON INVERTING
s HIGH SPEED: tPD = 6 ns (TYP.) at VCC = 3.3V
s COMPATIBLE WITH TTL OUTPUTS
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
s LOW NOISE: VOLP = 0.4V (TYP.) at VCC = 3.3V
s 75TRANSMISSION LINE OUTPUT DRIVE
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 12 mA (MIN)
s PCI BUS LEVELS GUARANTEED AT 24mA
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 3.6V (1.2VData Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The LVQ373 is a low voltage CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUTS NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C2MOS
technology. It is ideal for low power and low noise
3.3V applications.
These 8 bit D-Type latchs are controlled by a
latch enable input (LE) and an output enable
PIN CONNECTION AND IEC LOGIC SYMBOLS
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVQ373M
74LVQ373T
input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely.
When the LE is taken low, the Q outputs will be
latched precisely at the logic level of D input data.
While the (OE) input is low, the 8 outputs will be
in a normal logic state (high or low logic level)
and while high level the outputs will be in a high
impedance state.
It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
power consuption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
February 1999
1/10
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