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74LVQ08M 데이터 시트보기 (PDF) - STMicroelectronics

부품명74LVQ08M ST-Microelectronics
STMicroelectronics ST-Microelectronics
상세내역QUAD 2-INPUT AND GATE
74LVQ08M Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
74LVQ08
DC SPECIFICATIONS
Symb ol
Parameter
Test Conditions
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
VIH High Level Input Voltage 3.0 to
VIL Low Level Input Voltage
3.6
2.0
2.0
0.8
0.8
VOH High Level Output
Voltage
VOL Low Level Output
Voltage
II Input Leakage Current
3.0
VI(* ) = IO=-50 µA 2.9 2.99
VIH IO=-12 mA 2.58
2.9
2.48
IO=-24 mA
2.2
3.0
VI(*) = IO=50 µA
0.002 0.1
0.1
VIH or
VIL
IO=12 mA
IO=24 mA
0 0.36
0.44
0.55
3.6
VI = VCC or GND
±0.1
±1
ICC Quiescent Supply
Current
3.6
VI = VCC or GND
2
20
IOLD Dynamic Output Current
3.6
VOLD = 0.8 V max
36
IOHD (note 1, 2)
VOHD = 2 V min
-25
1) Maximum test duration 2ms, one output loaded attime
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50 .
(*) All outputs loaded.
Unit
V
V
V
V
µA
µA
mA
mA
DYNAMIC SWITCHING CHARACTERISTICS
Symb ol
Parameter
Test Conditions
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
Unit
VOLP Dynamic Low Voltage
3.3
VOLV Quiet Output (note 1, 2)
0.3 0.8
-0.8 -0.3
VIHD Dynamic High Voltage
3.3
Input (note 1, 3)
CL = 50 pF
2
V
VILD Dynamic Low Voltage
3.3
0.8
Input (note 1, 3)
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n -1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD).,f=1MHz.
3/8
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DESCRIPTION
The LVQ08 is a low voltage CMOS QUAD 2-INPUT AND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.It is ideal for low power and low noise 3.3V applications.
The internal circuit is composed of 2 stages including buffer output, which enables high noise immunity and stable output.
It has better speed performance at 3.3V than 5V LS-TTL family combined with the true CMOS low power consumption.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 3.3V
■ COMPATIBLEWITH TTL OUTPUTS
■ LOW POWER DISSIPATION:
   ICC =2 µA (MAX.) at TA = 25 °C
■ LOW NOISE:
   VOLP = 0.3 V (TYP.) at VCC = 3.3V
■ 75Ω TRANSMISSIONLINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 24 mA (MIN)
■ PCI BUS LEVELSGUARANTEED AT 24mA
■ BALANCEDPROPAGATIONDELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGERANGE:
   VCC (OPR)= 2V to 3.6V (1.2VData Retention)
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 08
■ IMPROVED LATCH-UP IMMUNITY

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