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74LVQ08M 데이터 시트보기 (PDF) - STMicroelectronics

부품명74LVQ08M ST-Microelectronics
STMicroelectronics ST-Microelectronics
상세내역QUAD 2-INPUT AND GATE
74LVQ08M Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
®
74LVQ08
QUAD 2-INPUT AND GATE
s HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 3.3V
s COMPATIBLE WITH TTL OUTPUTS
s LOW POWER DISSIPATION:
ICC = 2 µA (MAX.) at TA = 25 oC
s LOW NOISE:
VOLP = 0.3 V (TYP.) at VCC = 3.3V
s 75TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24 mA (MIN)
s PCI BUS LEVELS GUARANTEED AT 24mA
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 08
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The LVQ08 is a low voltage CMOS QUAD
2-INPUT AND GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C2MOS
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVQ08M
74LVQ08T
technology. It is ideal for low power and low noise
3.3V applications.
The internal circuit is composed of 2 stages
including buffer output, which enables high noise
immunity and stable output.
It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 1999
1/8
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DESCRIPTION
The LVQ08 is a low voltage CMOS QUAD 2-INPUT AND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.It is ideal for low power and low noise 3.3V applications.
The internal circuit is composed of 2 stages including buffer output, which enables high noise immunity and stable output.
It has better speed performance at 3.3V than 5V LS-TTL family combined with the true CMOS low power consumption.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 3.3V
■ COMPATIBLEWITH TTL OUTPUTS
■ LOW POWER DISSIPATION:
   ICC =2 µA (MAX.) at TA = 25 °C
■ LOW NOISE:
   VOLP = 0.3 V (TYP.) at VCC = 3.3V
■ 75Ω TRANSMISSIONLINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 24 mA (MIN)
■ PCI BUS LEVELSGUARANTEED AT 24mA
■ BALANCEDPROPAGATIONDELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGERANGE:
   VCC (OPR)= 2V to 3.6V (1.2VData Retention)
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 08
■ IMPROVED LATCH-UP IMMUNITY

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