BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
1 0 1 0 A6 A5
A1 A0 D15 D14
Fig. 4 Write cycle timing (WRITE)
tE / W
,,, 1 2
1 0 001
Fig. 5 Write all address cycle timing (WRAL)
tE / W
After time tCS following the fall of CS, after input of the
write command), if CS is set to HIGH, the write execute
= BUSY (LOW) and the command wait status READY
(HIGH) are output.
If in the command wait status (STATUS = READY), the
next command can be performed within the time tE / W.
Thus, if data is input via SK and DI with CS = HIGH in
the tE / W period, erroneous operations may be per-
formed. To avoid this, make sure that DI = LOW when
CS = HIGH. (Caution is especially important when
common input ports are used.) This applies to all of the
(7) All address write (Figure 5)
With this command, the input 16-bit data is written
simultaneously to all of the addresses (128 words).
Rather than writing one word at a time, in succession,
data is written all at one time, enabling a write time of
tE / W.
(8) Write disable (Figure 6)
When the power supply is turned on, the IC enters the
write disable status when a write enable command is
issued. If a write disable command is issued at this
point, however, the IC enters the write disabled status,
just as when the power is first turned on. Subsequent
write commands are cancelled by the software, but
read commands may be executed. In the write enable
status, writing begins even if a write command is
entered accidentally. To prevent errors of this type, we
recommend executing a write disable command after
writing has been completed.
Fig. 6 Write disable cycle timing (WDS)