datasheetbank_Logo    Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site
Part Name :

BR93LC56FV View Datasheet(PDF) - ROHM Semiconductor

Part NameBR93LC56FV ROHM
ROHM Semiconductor ROHM
Description2,048-Bit Serial Electrically Erasable PROM


BR93LC56FV Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Memory ICs
BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
CS
SK
12
4
11 12
tCS
STATUS
27
DI
1 0 1 0 A6 A5
A1 A0 D15 D14
D1 D0
DO
High-Z
Fig. 4 Write cycle timing (WRITE)
tSV
BUSY READY
tE / W
CS
tCS
STATUS
SK
DI
,,, 1 2
5
1 0 001
DO
High-Z
12
D15 D14
27
D1 D0
Fig. 5 Write all address cycle timing (WRAL)
tSV
BUSY READY
tE / W
(STATUS)
After time tCS following the fall of CS, after input of the
write command), if CS is set to HIGH, the write execute
= BUSY (LOW) and the command wait status READY
(HIGH) are output.
If in the command wait status (STATUS = READY), the
next command can be performed within the time tE / W.
Thus, if data is input via SK and DI with CS = HIGH in
the tE / W period, erroneous operations may be per-
formed. To avoid this, make sure that DI = LOW when
CS = HIGH. (Caution is especially important when
common input ports are used.) This applies to all of the
write commands.
(7) All address write (Figure 5)
With this command, the input 16-bit data is written
simultaneously to all of the addresses (128 words).
CS
SK
Rather than writing one word at a time, in succession,
data is written all at one time, enabling a write time of
tE / W.
(8) Write disable (Figure 6)
When the power supply is turned on, the IC enters the
write disable status when a write enable command is
issued. If a write disable command is issued at this
point, however, the IC enters the write disabled status,
just as when the power is first turned on. Subsequent
write commands are cancelled by the software, but
read commands may be executed. In the write enable
status, writing begins even if a write command is
entered accidentally. To prevent errors of this type, we
recommend executing a write disable command after
writing has been completed.
DI
1 0000
DO
High-Z
Fig. 6 Write disable cycle timing (WDS)
8
Direct download click here

•Overview
The BR93LC56 is CMOS serial input / output-type memory circuits (EEPROMs) that can be programmed electrically. Each is configured of 128 words × 16 bits (2,048 bits), and each word can be accessed individually and data read from it and written to it.

•Features
• Low power CMOS technology
• 128 × 16 bit configuration
• 2.7V to 5.5V operation
• Low power dissipation
– 3mA (max.) active current: 5V
– 5µA (max.) standby current: 5V
• Auto increment for efficient data bump
• Automatic erase-before-write
• Hardware and software write protection
– Default to write-disabled state at power up
– Software instructions for write-enable / disable
– Vcc lock out inadvertent write protection
• 8-pin SOP / 8-pin SSOP-B / 8-pin DIP packages
• Device status signal during write cycle
• TTL compatible Input / Output
• 100,000 ERASE / write cycles
• 10 years Data Retention

 

Share Link : ROHM

@ 2014 - 2018  [ Home ] [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]