BR93LC56FV View Datasheet(PDF) - ROHM Semiconductor

Part Name

Description

View to exact match

BR93LC56FV

2,048-Bit Serial Electrically Erasable PROM

ROHM Semiconductor 

Memory ICs

BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV

•Circuit operation

(1) Command mode

With these ICs, commands are not rec-

ognized or acted upon until the start bit

is received. The start bit is taken as the

first “1” that is received after the CS pin

rises.

Command

Read (READ)∗1

Start Operating

bit code

1

10

Address

0A6 ~ A0

Data

—

Write enabled (WEN)

1

00 11XXXXXX —

Write (WRITE)∗2

1

01

0A6 ~ A0 D15 ~ D0

Write all addresses (WRAL)∗2 1

00 01XXXXXX D15 ~ D0

∗1 After setting of the read command

Write disabled (WDS)

1

00 00XXXXXX —

and input of the SK clock, data corre-

sponding to the specified address is

output, with data corresponding to up-

per addresses then output in se-

Erase (ERASE)∗3

Chip erase (ERAL)∗3

1

11

0A6 ~ A0

—

1

00 10XXXXXX —

X: Either VIH or VIL

quence. (Auto increment function)

∗2 When the write or write all addresses command is executed, all data in the selected memory cell is erased auto-

matically, and the input data is written to the cell.

∗3 These modes are optional modes. Please contact Rohm for information on operation timing.

(2) Operation timing characteristics

(unless otherwise noted, Ta = – 40 to + 85°C, VCC = 5V ± 10%)

Parameter

Symbol Min.

SK clock frequency

fSK

—

SK "H" time

tSKH

450

SK "L" time

tSKL

450

CS "L" time

tCS

450

CS setup time

tCSS

50

DI setup time

tDIS

100

CS hold time

tCSH

0

DI hold time

tDIH

100

Data "1" output delay time

tPD1

—

Data "0" output delay time

tPD0

—

Time from CS to output confirmation

tSV

—

Time from CS to output High impedance tDF

—

Write cycle time

tE / W

—

Typ.

—

—

—

—

—

—

—

—

—

—

—

—

—

Max.

1

—

—

—

—

—

—

—

500

500

500

100

10

Unit

MHz

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ms

4

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