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BR93LC56FV View Datasheet(PDF) - ROHM Semiconductor

Part NameBR93LC56FV ROHM
ROHM Semiconductor ROHM
Description2,048-Bit Serial Electrically Erasable PROM

BR93LC56FV Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Memory ICs
BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
(2) Timing in the standby mode
As shown in Figure 8, during standby, if CS rises when
SK is HIGH, the DI state may be read on the rising
edge. If this happens, and DI is HIGH, this is taken to
be the start bit, causing a bit error (see point “a” in
Figure 8).
Make sure all inputs are LOW during standby or when
turning the power supply on or off (see Figure 9).
Point a: Start bit position during erroneous operation
Point b: Timing during normal operation
Fig. 8 Erroneous operation timing
Fig. 9 Normal operation timing
(3) Precautions when turning power on and off
When turning the power supply on and off, make sure
CS is set to LOW (see Figure 10).
When CS is HIGH, the EEPROM enters the active
state. To avoid this, make sure CS is set to LOW (dis-
able mode) when turning on the power supply.
(When CS is LOW, all input is cancelled.)
When the power supply is turned off, the low power
state can continue for a long time because of the
capacity of the power supply line. Erroneous opera-
tions and erroneous writing can occur at such times for
the same reasons as described above. To avoid this,
make sure CS is set to LOW before turning off the
power supply.
To prevent erroneous writing, these ICs are equipped
with a POR (Power On Reset) circuit, but in order to
achieve operation at a low power supply, VCC is set to
operate at approximately 1.3V. After the POR has been
activated, writing is disabled, but if CS is set to HIGH,
writing may be enabled because of noise or other fac-
tors. However, the POR circuit is effective only when
the power supply is on, and will not operate when the
power is off.
Also, to prevent erroneous writing at low voltages,
these ICs are equipped with a built-in circuit (VCC-lock-
out circuit) which resets the write command if VCC
drops to approximately 2V or lower (typ.) ().
+ 5V
+ 5V
Bad example
Good example
(Bad example) Here, the CS pin is pulled up to VCC. In this case, CS is
HIGH (active state). Please be aware that the EEPROM
may perform erroneous operations or write erroneous
data because of noise or other factors. This can occur
even if the CS input is high-Z.
(Good example) In this case, CS is LOW when the power supply is
turned on or off.
Fig. 10
(4) Clock (SK) rise conditions
If the clock pin (SK) signal of the BR93LC56 / F / FV
has a long rise time (tr) and if noise on the signal line
exceeds a certain level, erroneous operation can occur
due to erroneous counts in the clock. To prevent this, a
Schmitt trigger is built into the SK input of the BR93-
LC56 / F / FV. The hysteresis amplitude of this circuit is
set to approximately 0.2V, so if the noise exceeds the
SK input, the noise amplitude should be set to 0.2VP-P
or lower. Furthermore, rises and falls in the clock input
should be accelerated as much as possible.
(5) Power supply noise
The BR93LC56 / F / FV discharge high volumes of high
voltage when a write is completed. The power supply
may fluctuate at such times. Therefore, make sure a
capacitor of 1000pF or greater is connected between
VCC (Pin 8) and GND (Pin 5).
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The BR93LC56 is CMOS serial input / output-type memory circuits (EEPROMs) that can be programmed electrically. Each is configured of 128 words × 16 bits (2,048 bits), and each word can be accessed individually and data read from it and written to it.

• Low power CMOS technology
• 128 × 16 bit configuration
• 2.7V to 5.5V operation
• Low power dissipation
– 3mA (max.) active current: 5V
– 5µA (max.) standby current: 5V
• Auto increment for efficient data bump
• Automatic erase-before-write
• Hardware and software write protection
– Default to write-disabled state at power up
– Software instructions for write-enable / disable
– Vcc lock out inadvertent write protection
• 8-pin SOP / 8-pin SSOP-B / 8-pin DIP packages
• Device status signal during write cycle
• TTL compatible Input / Output
• 100,000 ERASE / write cycles
• 10 years Data Retention


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