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74LV574 View Datasheet(PDF) - Philips Electronics

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74LV574 Datasheet PDF : 12 Pages
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Philips Semiconductors
Octal D-type flip-flop; positive edge-trigger (3-State)
Product specification
74LV574
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V and v 3.6V
VM = 0.5 * VCC at VCC t 2.7V and w 4.5V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VX = VOL + 0.3V at VCC w 2.7V and v 3.6V
VX = VOL + 0.1VCC at VCC < 2.7V and w 4.5V
VY = VOH – 0.3V at VCC w 2.7V and v 3.6V
VY = VOH – 0.1VCC at VCC < 2.7V and w 4.5V
VI
CP INPUT
GND
VOH
Qn OUTPUT
VOL
1/fmax
VM
tW
tPHL
VM
tPLH
SV00718
Figure 1. Clock (CP) to output (Qn) propagation delays, the
clock pulse (CP) and the maximum clock pulse frequency
VI
OE INPUT
GND
VCC
OUTPUT
LOW-to-OFF
OFF-to-LOW
VOL
VM
tPLZ
VX
tPHZ
tPZL
VM
tPZH
VOH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
VY
outputs
enabled
outputs
disabled
VM
outputs
enabled
SV00344
Figure 2. 3-state enable and disable times
VI
CP INPUT
VM(1)
GND
tsu
tsu
VI
ÏÏÏÏ Dn INPUT
VM
ÏÏÏÏÏÏÏÏ GND
ÏÏÏth ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏthÏÏÏ
VOH
Qn OUTPUT
VM
VOL
NOTE: the shaded areas indicate when the input is permitted to change
for predictable output performance.
SV00345
Figure 3. Data set-up and hold times for the Dn input to the CP
input
NOTE:
The shaded areas indicate when the input is permitted to change for
predictable output performance.
TEST CIRCUIT
PULSE
GENERATOR
VI
RT
VCC
D.U.T.
VO
CL 50 pF
2 * VCC
Open
GND
RL = 1k
RL = 1k
Test Circuit for Outputs
DEFINITIONS
RL = Load resistor
CL = Load capacitance includes jig and probe capacitiance.
RT = Termination resistance should be equal to ZOUT of pulse generators.
SWITCH POSITION
TEST
S1
VCC
VI
tPLH/tPHL
Open
< 2.7V
VCC
tPLZ/tPZL
tPHZ/tPZH
2 * VCC
GND
2.7–3.6V
w 4.5V
2.7V
VCC
SV00896
Figure 4. Load circuitry for switching times
1998 Jun 10
7
 

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