74LV4053D View Datasheet(PDF) - Philips Electronics
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Description
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74LV4053D Datasheet PDF : 16 Pages
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Philips Semiconductors
Triple 2-channel analog multiplexer/demultiplexer
Product specification
74LV4053
FEATURES
• Optimized for low voltage applications: 1.0 to 6.0 V
• Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
• Low typ “ON” resistance:
100 W at Vcc – VEE = 4.5 V
150 W at Vcc – VEE = 3.0 V
240 W at Vcc – VEE = 2.0 V
• Logic level translation: to enable 3 V logic to communicate with ± 3
V analog signals
• Typical “break before make” built in
• Output capability: non-standard
• ICC category: MSI
DESCRIPTION
The 74LV4053 is a low-voltage CMOS device and is pin and
function compatible with the 74HC/HCT4053.
The 74LV4053 is a triple 2-channel analog multiplexer/demultiplexer with
a common enable input (E). Each multiplexer/demultiplexer has two
independent inputs/outputs (nY0 to nY1), a common input/output (nZ)
and three digital select inputs (S1 to S3).
With E LOW, one of the two switches is selected (low impedance
ON-state) by S1 to S3 With E HIGH, all switches are in the high
impedance OFF-states, independent of S1 and S3.
VCC and GND are the supply voltage pins for the digital control inputs
(S1, to S3, and E). The VCC to GND ranges are 1.0 to 6.0 V. The
analog inputs/outputs (nY0, to nY1, and nZ) can swing between VCC
as a positive limit and VEE as a negative limit. VCC - VEE may not
exceed 6.0 V. For operation as a digital multiplexer/demultiplexer, VEE
is connected to GND (typically ground).
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr =tf ≤ 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
tPZH/tPZL
Turn “ON” time
E to VOS
Sn to VOS
CL = 15 pF
RL = 1KW
VCC = 3.3 V
tPHZ/tPLZ
Turn “OFF” time
E to VOS
Sn to VOS
CI
Input capacitance
CPD
Power dissipation capacitance per switch See Notes 1 and 2
CS
Maximum switch capacitance
independent (Y) common (Z)
NOTES:
1.
CPD is used
PD = CPD ×
VtoCCd2et×erfmi )inȍe
the dynamic
((CL + CS) ×
power dissipation
VCC2 × fo) where:
(PD
in
µW)
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; CS = maximum switch capacitance in pF;
VȍC(C(C=L
supply voltage
+CS) × VCC2 ×
in V;
fo) =
sum
of
the
outputs.
2. The condition is VI = GND to VCC.
TYPICAL
16
20
17
16
3.5
36
5
8
UNIT
ns
pF
ORDERING INFORMATION
PACKAGES
16-Pin Plastic DIL
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
OUTSIDE NORTH AMERICA
74LV4053 N
74LV4053 D
74LV4053 DB
74LV4053 PW
NORTH AMERICA
74LV4053 N
74LV4053 D
74LV4053 DB
74LV4053PW DH
PKG. DWG. #
SOT38-1
SOT109-1
SOT338-1
SOT403-1
PIN CONFIGURATION
2Y1 1
2Y0 2
3Y1 3
3Z 4
3Y0 5
E6
VEE 7
GND 8
16 VCC
15 2Z
14 1Z
13 1Y1
12 1Y0
11 S1
10 S2
9 S3
SV01687
PIN DESCRIPTION
PIN NUMBER SYMBOL
2, 1
2Y0, 2Y1
5, 3
3Y0, 3Y1
6
E
7
VEE
8
GND
11, 10, 9
12, 13
14, 15, 4
S1 to S3
1Y0, 1Y1
1Z to 3Z
16
VCC
FUNCTION
Independent inputs/outputs
Independent inputs/outputs
Enable input (active LOW)
Negative supply voltage
Ground (0 V)
Select inputs
Independent inputs/outputs
Common inputs/outputs
Positive supply voltage
1998 Jun 23
2
853-2000 19618
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