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74LV393 View Datasheet(PDF) - Philips Electronics

Part NameDescriptionManufacturer
74LV393 Dual 4-bit binary ripple counter Philips
Philips Electronics Philips
74LV393 Datasheet PDF : 12 Pages
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Philips Semiconductors
Dual 4-bit binary ripple counter
Product specification
74LV393
FEATURES
Optimized for Low Voltage applications: 1.0 to 3.6V
Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V
Typical VOLP (output ground bounce) t 0.8V @ VCC = 3.3V,
Tamb = 25°C
Typical VOHV (output VOH undershoot) u 2V @ VCC = 3.3V,
Tamb = 25°C
Two 4-bit binary counters with individual clocks
Divide-by any binary module up to 28 in one package
Two master resets to clear each 4-bit counter individually
Output capability: standard
ICC category: MSI
DESCRIPTION
The 74LV393 is a low–voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT393.
The 74LV393 is a dual 4-bit binary ripple counter with separate
clocks (1CP, 2CP) and master reset (1MR, 2MR) inputs to each
counter.
The operation of each half of the ‘‘393’’ is the same as the ‘‘93’’
except no external clock connections are required. The counters are
triggered by a HIGH-to-LOW transition of the clock inputs. The
counter outputs are internally connected to provide clock inputs to
succeeding stages. The outputs of the ripple counter do not change
synchronously and should not be used for high-speed address
decoding.
The master resets are active-HIGH asynchronous inputs to each
4-bit counter identified by the ‘‘1’’ and ‘‘2’’ in the pin description.
A HIGH level on the nMR input overrides the clock and sets the
outputs LOW.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf v2.5 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
Propagation delay
nCP to nQ0
nQ to nQn+1
nMR to nQn
CL = 15pF
VCC = 3.3V
fmax
Maximum clock frequency
CI
Input capacitance
CPD
Power dissipation capacitance per flip-flop VI = GND to VCC 1
NOTE:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD VCC2 fi )S (CL VCC2 fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL VCC2 fo) = sum of the outputs.
TYPICAL
12
4
11
99
3.5
23
ORDERING INFORMATION
PACKAGES
14-Pin Plastic DIL
14-Pin Plastic SO
14-Pin Plastic SSOP Type II
14-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
OUTSIDE NORTH AMERICA
74LV393 N
74LV393 D
74LV393 DB
74LV393 PW
NORTH AMERICA
74LV393 N
74LV393 D
74LV393 DB
74LV393PW DH
UNIT
ns
MHz
pF
pF
PKG. DWG. #
SOT27-1
SOT108-1
SOT337-1
SOT402-1
PIN CONFIGURATION
1CP 1
1MR 2
1Q0 3
1Q1 4
1Q2 5
1Q3 6
GND 7
14 VCC
13 2CP
12 2MR
11 2Q0
10 2Q1
9 2Q2
8 2Q3
SV00672
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
1, 13
1CP, 2CP
2, 12
3, 4, 5, 6
11, 10, 9, 8
7
14
1MR, 2MR
1Q0 to 1Q3
2Q0 to 2Q3
GND
VCC
FUNCTION
Clock inputs
(HIGH-to-LOW, edge-triggered)
Asynchronous master reset inputs
(active HIGH)
Flip-flop outputs
Ground (0V)
Positive supply voltage
1998 Jun 10
2
853–1936 19545
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