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74LV138PWDH View Datasheet(PDF) - Philips Electronics

Part Name
Description
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74LV138PWDH
Philips
Philips Electronics Philips
74LV138PWDH Datasheet PDF : 12 Pages
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Philips Semiconductors
3-to-8 line decoder/demultiplexer; inverting
Product specification
74LV138
FEATURES
Wide operating voltage: 1.0 to 5.5 V
Optimized for low voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V,
Tamb = 25°C
Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V,
Tamb = 25°C
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Active LOW mutually exclusive outputs
Output capability: standard
ICC category: MSI
DESCRIPTION
The 74LV138 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT138.
The 74LV138 accepts three binary weighted address inputs (A0, A1,
A2) and when enabled, provide 8 mutually exclusive active LOW
outputs (Y0 to Y7).
The 74LV138 features three enable inputs: two active LOW (E1, and
E2) and one active HIGH (E3). Every output will be HIGH unless E1
and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion of the
74LV138 to a 1-of-32 (5 lines to 32 lines) decoder with just four
74LV138 ICs and one inverter. The 74LV138 can be used as an
eight output demultiplexer by using one of the active LOW enable
inputs as the data input and the remaining enable inputs as strobes.
Unused enable inputs must be permanently tied to their appropriate
active HIGH or LOW state. The 74LV138 is identical to the 74LV238
but has non-inverting (true) outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
Propagation delay
An to Yn,
E3 to Yn, En to Yn
CL = 15 pF;
VCC = 3.3 V
CI
Input capacitance
CPD
Power dissipation capacitance per
package
VCC = 3.3 V
VI = GND to VCC1
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
ȍ (CL × VCC2 × fo) = sum of the outputs.
TYPICAL
12
14
3.5
45
ORDERING INFORMATION
PACKAGES
16-Pin Plastic DIL
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
OUTSIDE NORTH AMERICA
74LV138 N
74LV138 D
74LV138 DB
74LV138 PW
NORTH AMERICA
74LV138 N
74LV138 D
74LV138 DB
74LV138PW DH
UNIT
ns
ns
pF
pF
PKG. DWG. #
SOT38-4
SOT109-1
SOT338-1
SOT403-1
PIN CONFIGURATION
A0 1
A1 2
A2 3
E1 4
E2 5
E3 6
Y7 7
GND 8
16 VCC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
PIN DESCRIPTION
PIN NUMBER SYMBOL
1, 2, 3
4, 5
6
15, 14, 13, 12,
11, 10, 9, 7
A0 to A2
E1 to E2
E3
Y0 to Y7
8
GND
16
VCC
FUNCTION
Address inputs
Enable inputs (active LOW)
Enable inputs (active HIGH)
Outputs
Ground (0 V)
Positive supply voltage
SV00524
1998 Apr 28
2
853–1903 19290
 

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