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54LS191J View Datasheet(PDF) - Motorola => Freescale

Part NameDescriptionManufacturer
54LS191J PRESETTABLE BCD/DECADE PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS Motorola
Motorola => Freescale Motorola
54LS191J Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
SN54/74LS190 SN54/74LS191
AC CHARACTERISTICS (TA = 25°C)
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Parameter
Maximum Clock Frequency
Propagation Delay,
PL to Output Q
Data to Output Q
Clock to RC
Clock to Output Q
Clock to TC
U / D to RC
U / D to TC
CE to RC
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
tW
tW
ts
th
trec
Parameter
CP Pulse Width
PL Pulse Width
Data Setup Time
Data Hold Time
Recovery Time
Limits
Min Typ Max
20
25
22
33
33
50
20
32
27
40
13
20
16
24
16
24
24
36
28
42
37
52
30
45
30
45
21
33
22
33
21
33
22
33
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Limits
Min Typ Max Unit
25
ns
35
ns
20
ns
5.0
ns
40
ns
Test Conditions
VCC = 5.0 V
CL = 15 pF
Test Conditions
VCC = 5.0 V
DEFINITIONS OF TERMS
SETUP TIME (ts) is defined as the minimum time required for
the correct logic level to be present at the logic input prior to the
clock transition from LOW-to-HIGH in order to be recognized
and transferred to the outputs.
HOLD TIME (th) is defined as the minimum time following the
clock transition from LOW-to-HIGH that the logic level must be
maintained at the input in order to ensure continued recogni-
tion. A negative HOLD TIME indicates that the correct logic
level may be released prior to the clock transition from LOW-
to-HIGH and still be recognized.
RECOVERY TIME (trec) is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer HIGH data to the Q outputs.
FAST AND LS TTL DATA
5-346
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