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74LV107DB View Datasheet(PDF) - Philips Electronics

Part Name
Description
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74LV107DB Datasheet PDF : 12 Pages
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Philips Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
Product specification
74LV107
AC WAVEFORMS
VM = 1.5 V at VCC 2.7 V and 3.6 V;
VM = 0.5 × VCC at VCC < 2.7 V and 4.5 V;
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI
nJ, nK
INPUT
GND
VI
nCP
INPUT
GND
VOH
nQ
OUTPUT
VOL
VOH
nQ
OUTPUT
VOL
VM
t su
th
1/f max
VM
tW
t PHL
VM
VM
t su
th
t PLH
t PLH
t PHL
The shaded areas indicate when the input is permitted to change for
predictable output performance.
SV00504
Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays,
the clock pulse width, the J and K to nCP set-up and hold times
and the maximum clock pulse frequency.
TEST CIRCUIT
Vcc
PULSE
GENERATOR
Vl
RT
D.U.T.
VO
50pF
CL
RL= 1k
Test Circuit for Outputs
DEFINITIONS
RL = Load resistor
CL = Load capacitance includes jig and probe capacitiance
RT = Termination resistance should be equal to ZOUT of pulse generators.
TEST
tPLH/tPHL
VCC
< 2.7V
2.7–3.6V
4.5 V
VI
VCC
2.7V
VCC
SV00902
Figure 3. Load circuitry for switching times.
VI
nCP
INPUT
GND
VI
nR
INPUT
GND
tW
VM
VM
t rem
VOH
nQ
OUTPUT
VOL
VOH
nQ
OUTPUT
VOL
t PHL
VM
t PLH
SV00502
Figure 2. Reset (nR) input to output (nQ, nQ) propagation
delays, the reset pulse width and the nR to nCP removal time.
1998 Apr 20
7
 

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