74HCT3G07 View Datasheet(PDF) - NXP Semiconductors.
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74HCT3G07 Datasheet PDF : 13 Pages
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NXP Semiconductors
74HC3G07; 74HCT3G07
Triple buffer with open-drain outputs
VI 90 %
tW
negative
pulse
VM
10 %
0V
tf
VI
positive
pulse
tr
90 %
VM
10 %
0V
tW
VM
tr
tf
VM
VI
G
VCC
VO
DUT
RT
VCC
RL S1
CL
open
001aad983
Fig 7.
Test data is given in Table 10.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Test circuit for measuring switching times
Table 10. Test data
Type
Input
74HC3G07
74HCT3G07
VI
GND to VCC
GND to 3 V
tr, tf
≤ 6 ns
≤ 6 ns
Load
CL
50 pF
50 pF
RL
1 kΩ
1 kΩ
S1 position
tPZL, tPLZ
VCC
VCC
74HC_HCT3G07_2
Product data sheet
Rev. 02 — 12 May 2009
© NXP B.V. 2009. All rights reserved.
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