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74HCT4024D View Datasheet(PDF) - Philips Electronics

Part Name
Description
View to exact match
74HCT4024D
Philips
Philips Electronics Philips
74HCT4024D Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
Philips Semiconductors
7-stage binary ripple counter
Product specification
74HC/HCT4024
FEATURES
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4024 are high-speed Si-gate CMOS
devices and are pin compatible with the “4024” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4024 are 7-stage binary ripple counters
with a clock input (CP), an overriding asynchronous
master reset input (MR) and seven fully buffered parallel
outputs (Q0 to Q6).
The counter advances on the HIGH-to-LOW transition of
CP.
A HIGH on MR clears all counter stages and forces all
outputs LOW, independent of the state of CP.
Each counter stage is a static toggle flip-flop.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
APPLICATIONS
Frequency dividing circuits
Time delay circuits
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/ tPLH
fmax
CI
CPD
propagation delay CP to Q0
maximum clock frequency
input capacitance
power dissipation capacitance per package
CL = 15 pF; VCC = 5 V
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
(CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
TYPICAL
HC
14
90
3.5
25
HCT
14
70
3.5
27
UNIT
ns
MHz
pF
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
 

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