74HC112N View Datasheet(PDF) - Philips Electronics

Part Name

Description

View to exact match

74HC112N

Dual JK flip-flop with set and reset; negative-edge trigger

Philips Electronics 

Philips Semiconductors

Dual JK flip-flop with set and reset;

negative-edge trigger

AC WAVEFORMS

Product specification

74HC/HCT112

(1) HC : VM = 50%; VI = GND to VCC.

HCT: VM = 1.3 V; VI = GND to 3 V.

The shaded areas indicate when the input is permitted to

change for predictable output performance.

Fig.6 Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width,

the nJ, nK to nCP set-up times, the nCP to nJ, nK hold times, the output transition times and the maximum

clock pulse frequency.

handbook, full pagewidth

nCP INPUT

VM(1)

trem

nSD INPUT

nRD INPUT

VM(1)

tW

tPLH

trem

tW

VM(1)

tPHL

nQ OUTPUT

VM(1)

tPHL

tPLH

nQ OUTPUT

(1) HC : VM = 50%; VI = GND to VCC.

HCT: VM = 1.3 V; VI = GND to 3 V.

VM(1)

MBK218

Fig.7 Waveforms showing the set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set

and reset pulse width and the nRD and nSD to nCP removal time.

1998 Jun 10

9

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