74HC73 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
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74HC73 Datasheet PDF : 16 Pages
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NXP Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
C
C
C
C
K
Q
J
C
C
C
C
R
Q
CP
C
C
Fig 4. Logic diagram (one flip-flop)
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5. Pinning information
5.1 Pinning
Fig 5. Pin configuration
1CP 1
1R 2
1K 3
VCC 4
2CP 5
2R 6
2J 7
74HC73
14 1J
13 1Q
12 1Q
11 GND
10 2K
9 2Q
8 2Q
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5.2 Pin description
Table 2. Pin description
Symbol
Pin
1CP, 2CP
1, 5
1R, 2R
2, 6
1K, 2K
3, 10
VCC
4
GND
11
1Q, 2Q
12, 9
1Q, 2Q
13, 8
1J, 2J
14, 7
Description
clock input (HIGH-to-LOW edge-triggered); also referred to as nCP
asynchronous reset input (active LOW); also referred to as nR
synchronous K input; also referred to as nK
positive supply voltage
ground (0 V)
true output; also referred to as nQ
complement output; also referred to as nQ
synchronous J input; also referred to as nJ
74HC73_4
Product data sheet
Rev. 04 — 19 March 2008
© NXP B.V. 2008. All rights reserved.
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