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74HC73U View Datasheet(PDF) - Philips Electronics

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74HC73U Datasheet PDF : 21 Pages
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Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
Table 3:
Symbol
GND
1Q
1Q
1J
Pin description …continued
Pin
Description
11
ground (0 V)
12
true flip-flop 1 output
13
complement flip-flop 1 output
14
synchronous J input for flip-flop 1
7. Functional description
7.1 Function table
Table 4: Function table [1]
Input
Output
Operating mode
nR
nCP
nJ
nK
nQ
nQ
L
X
X
X
L
H
asynchronous reset
H
h
h
q
q
toggle
l
h
L
H
load 0 (reset)
h
l
H
L
load 1 (set)
l
l
q
q
hold (no change)
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition;
q = state of referenced output one set-up time prior to the HIGH-to-LOW CP transition;
X = don’t care;
= HIGH-to-LOW CP transition.
8. Limiting values
9397 750 13815
Product data sheet
Table 5: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
VCC
supply voltage
0.5 +7 V
IIK
input diode current
VI < 0.5 V or VI > VCC + 0.5 V
-
±20 mA
IOK
output diode current
VO < 0.5 V or VO > VCC + 0.5 V
-
±20 mA
IO
output source or sink VO = 0.5 V to VCC + 0.5 V
current
-
±25 mA
ICC, IGND VCC or GND current
Tstg
storage temperature
-
±50 mA
65 +150 °C
Ptot
power dissipation
DIP14 package
[1] -
750 mW
SO14, SSOP14 and
TSSOP14 packages
[2] -
500 mW
[1] Above 70 °C: Ptot derates linearly with 12 mW/K.
[2] Above 70 °C: Ptot derates linearly with 8 mW/K.
Rev. 03 — 12 November 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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