74HCT299 View Datasheet(PDF) - NXP Semiconductors.
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74HCT299 Datasheet PDF : 24 Pages
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74HC299; 74HCT299
8-bit universal shift register; 3-state
Rev. 03 — 28 July 2008
Product data sheet
1. General description
The 74HC299; 74HCT299 are high-speed Si-gate CMOS devices which are
pin-compatible with Low-power Schottky TTL (LSTTL) devices. They are specified in
compliance with JEDEC standard no. 7A.
The 74HC299; 74HCT299 contain eight edge-triggered D-type flip-flops and the
interstage logic necessary to perform synchronous shift-right, shift-left, parallel load and
hold operations. An operation is determined by the mode select inputs S0 and S1, as
shown in Table 3.
Pins I/O0 to I/O7 are flip-flop 3-state buffer outputs which allow them to operate as data
inputs in parallel load mode. The serial outputs Q0 and Q7 are used for expansion in
serial shifting of longer words.
A LOW signal on the asynchronous master reset input MR overrides the Sn and clock CP
inputs and resets the flip-flops. All other state changes are initiated by the rising edge of
the clock pulse. Inputs can change when the clock is in either state, provided that the
recommended set-up and hold times are observed.
A HIGH signal on the 3-state output enable inputs OE1 or OE2 disables the 3-state
buffers and the I/On outputs are set to the high-impedance OFF-state. In this condition,
the shift, hold, load and reset operations still occur when preparing for a parallel load
operation. The 3-state buffers are also disabled by HIGH signals on both S0 and S1.
2. Features
I Multiplexed inputs/outputs provide improved bit density
I Four operating modes:
N Shift left
N Shift right
N Hold (store)
N Load data
I Operates with output enable or at high-impedance OFF-state (Z)
I 3-state outputs drive bus lines directly
I Cascadable for n-bit word lengths
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
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