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74HCT107D View Datasheet(PDF) - Philips Electronics

Part NameDescriptionManufacturer
74HCT107D Dual JK flip-flop with reset; negative-edge trigger Philips
Philips Electronics Philips
74HCT107D Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
Philips Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
Product specification
74HC/HCT107
FEATURES
Output capability: standard
ICC category: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT107 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT107 are dual negative-edge triggered
JK-type flip-flops featuring individual J, K, clock (nCP) and
reset (nR) inputs; also complementary Q and Q outputs.
The J and K inputs must be stable one set-up time prior to
the HIGH-to-LOW clock transition for predictable
operation.
The reset (nR) is an asynchronous active LOW input.
When LOW, it overrides the clock and data inputs, forcing
the Q output LOW and the Q output HIGH.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/ tPLH
fmax
CI
CPD
propagation delay
nCP to nQ
nCP to nQ
nR to nQ, nQ
maximum clock frequency
input capacitance
power dissipation
capacitance per flip-flop
CL = 15 pF;
VCC = 5 V
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
(CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V.
TYPICAL
HC
HCT
UNIT
16
16
ns
16
18
ns
16
17
ns
78
73
MHz
3.5
3.5
pF
30
30
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
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