74FR240 View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
View to exact match
74FR240 Datasheet PDF : 5 Pages
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October 1991
Revised August 1999
74FR240
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The 74FR240 is an inverting octal buffer and line driver
designed to be employed as memory and address driver,
clock driver and bus oriented transmitter or receiver.
Features
s 3-STATE outputs drive bus lines or buffer memory
address registers
s Outputs sink 64 mA and source 15 mA
s Guaranteed pin-to-pin skew
Ordering Code:
Order Number Package Number
Package Description
74FR240SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74FR240SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74FR240PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
Description
OE1, OE2
I0–I7
O0–O7
Output Enable Input (Active-LOW)
Inputs
Outputs
Truth Tables
Inputs
OE1
In
L
L
L
H
H
X
Outputs
(Pins 12, 14, 16, 18)
H
L
Z
Inputs
OE2
In
L
L
L
H
H
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Outputs
(Pins 3, 5, 7, 9)
H
L
Z
© 1999 Fairchild Semiconductor Corporation DS010901
www.fairchildsemi.com
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