datasheetbank_Logo     データシート検索エンジンとフリーデータシート

54F253LMX データシートの表示(PDF) - National ->Texas Instruments

部品番号コンポーネント説明メーカー
54F253LMX Dual 4-Input Multiplexer with TRI-STATE Outputs National-Semiconductor
National ->Texas Instruments National-Semiconductor
54F253LMX Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
Unit Loading Fan Out
Pin Names
I0a – I3a
I0b – I3b
S0 – S1
OEa
OEb
Za Zb
Description
Side A Data Inputs
Side B Data Inputs
Common Select Inputs
Side A Output Enable Input (Active LOW)
Side B Output Enable Input (Active LOW)
TRI-STATE Outputs
54F 74F
UL
HIGH LOW
10 10
10 10
10 10
10 10
10 10
150 40(33 3)
Input IIH IIL
Output IOH IOL
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b3 mA 24 mA (20 mA)
Functional Description
This device contains two identical 4-input multiplexers with
TRI-STATE outputs They select two bits from four sources
selected by common Select inputs (S0 S1) The 4-input mul-
tiplexers have individual Output Enable (OEa OEb) inputs
which when HIGH force the outputs to a high impedance
(High Z) state This device is the logic implementation of a
2-pole 4-position switch where the position of the switch is
determined by the logic levels supplied to the two select
inputs The logic equations for the outputs are shown below
Za e OEa  (I0a  S1  S0 a I1a  S1  S0 a
I2a  S1  S0 a I3a  S1  S0)
Zb e OEb  (I0b  S1  S0 a I1b  S1  S0 a
I2b  S1  S0 a I3b  S1  S0)
If the outputs of TRI-STATE devices are tied together all
but one device must be in the high impedance state to avoid
high currents that would exceed the maximum ratings De-
signers should ensure that Output Enable signals to TRI-
STATE devices whose outputs are tied together are de-
signed so that there is no overlap
Logic Diagram
Truth Table
Select
Inputs
S0 S1
XX
LL
LL
HL
Data Inputs
I0 I1 I2 I3
XXXX
LXXX
HXXX
XLXX
Output
Enable
OE
H
L
L
L
H L XHXX
L
L H XXLX
L
L H XXHX
L
H H XXXL
L
H H XXXH
L
Address inputs S0 and S1 are common to both sections
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Z e High Impedance
Output
Z
Z
L
H
L
H
L
H
L
H
TL F 9505 – 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2
Direct download click here

 

Share Link : 

All Rights Reserved © datasheetbank.com 2014 - 2019 [ 個人情報 保護方針 ] [ リクエストデータシート ]