74F139PC View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
View to exact match
74F139PC Datasheet PDF : 6 Pages
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Unit Loading/Fan Out
Pin Names
Description
U.L.
Input IIH/IIL
HIGH/LOW Output IOH/IOL
A0, A1
E
Address Inputs
Enable Inputs (Active LOW)
1.0/1.0
1.0/1.0
20 µA/−0.6 mA
20 µA/−0.6 mA
O0–O3
Outputs (Active LOW)
50/33.3 −1 mA/20 mA
Functional Description
The F139 is a high-speed dual 1-of-4 decoder/demulti-
plexer. The device has two independent decoders, each of
which accepts two binary weighted inputs (A0–A1) and pro-
vides four mutually exclusive active LOW Outputs (O0–O3).
Each decoder has an active LOW enable (E). When E is
HIGH all outputs are forced HIGH. The enable can be used
as the data input for a 4-output demultiplexer application.
Each half of the F139 generates all four minterms of two
variables. These four minterms are useful in some applica-
tions, replacing multiple gate functions as shown in
Figure 1, and thereby reducing the number of packages
required in a logic network.
Logic Diagram
FIGURE 1. Gate Functions (each half)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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