74F112CW View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
View to exact match
74F112CW Datasheet PDF : 7 Pages
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Unit Loading/Fan Out
Pin Names
Description
U.L.
Input IIH/IIL
HIGH/LOW Output IOH/IOL
J1, J2, K1, K2 Data Inputs
CP1, CP2
Clock Pulse Inputs (Active Falling Edge)
CD1, CD2
Direct Clear Inputs (Active LOW)
SD1, SD2
Direct Set Inputs (Active LOW)
Q1, Q2, Q1, Q2 Outputs
1.0/1.0
1.0/4.0
1.0/5.0
1.0/5.0
50/33.3
20 µA/−0.6 mA
20 µA/−2.4 mA
20 µA/−3.0 mA
20 µA/−3.0 mA
−1 mA/20 mA
Truth Table
Inputs
Outputs
SD
CD
CP
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H
H
H
H
H
H
h
l
h
h
Q0
L
Q0
H
H
H
h
l
H
L
H
H
l
l
Q0
Q0
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
X = Immaterial
= HIGH-to-LOW Clock Transition
Q0(Q0) = Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.
Logic Diagram
(One Half Shown)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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