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74F112 View Datasheet(PDF) - Philips Electronics

Part Name
Description
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74F112 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
Philips Semiconductors
Dual J-K negative edge-triggered flip-flop
Product specification
74F112
LOGIC SYMBOL
3 11 2 12
J0 J1 K0 K1
1
CP0
4
SD0
15
RD0
13
CP1
10
SD1
14
RD1
Q0 Q0 Q1 Q1
VCC = Pin 16
GND = Pin 8
LOGIC DIAGRAM
56 97
SF00104
IEC/IEEE SYMBOL
3
1J
1
C1
2
1K
15
R
4
S
11
2J
13
C2
12
2K
14
R
10
S
5
6
9
7
SF00105
5, 9
Qn
6, 7
Qn
4, 10
SDn
2, 12
Kn
15, 14
RDn
3, 11
Jn
VCC = Pin 16
GND = Pin 8
1, 13
CPn
SF00106
FUNCTION TABLE
INPUTS
OUTPUTS
SD
RD
CP
J
K
Q
Q
OPERATING MODE
L
H
X
X
X
H
L Asynchronous Set
H
L
X
X
X
L
H Asynchronous Reset
L
L
X
X
X
H*
H* Undetermined *
H
H
h
h
q
q Toggle
H
H
l
h
L
H Load “0” (Reset)
H
H
h
l
H
L Load “1” (Set)
H
H
l
l
q
q Hold “no change”
H
H
H
X
X
Q
Q Hold “no change”
H = High voltage level
h = High voltage level one setup time prior to High-to-Low clock transition
L = Low voltage level
l = Low voltage level one setup time prior to High-to-Low clock transition
q = Lower case letters indicate the state of the reference output prior to the High-to-Low clock transition
X = Don’t care
= High-to-Low clock transition
* = Both outputs will be High while both SD and RD are Low, but the output states are unpredictable if SD and RD go High simultaneously.
February 9, 1990
3
 

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