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74ALVCH16374DL,118 View Datasheet(PDF) - NXP Semiconductors.

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74ALVCH16374DL,118 Datasheet PDF : 17 Pages
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NXP Semiconductors
74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
5.2 Pin description
Table 2. Pin description
Symbol
Pin
1OE, 2OE
1, 24
1Q0 to 1Q7
2, 3, 5, 6, 8, 9, 11, 12
2Q0 to 2Q7
13, 14, 16, 17, 19, 20, 22, 23
GND
4, 10, 15, 21, 28, 34, 39, 45
VCC
1D0 to 1D7
7, 18, 31, 42
47, 46, 44, 43, 41, 40, 38, 37
2D0 to 2D7
36, 35, 33, 32, 30, 29, 27, 26
1CP, 2CP
48, 25
6. Functional description
Description
output enable input (active LOW)
3-state flip-flop outputs
3-state flip-flop outputs
ground (0 V)
positive supply voltage
data inputs
data inputs
clock input
6.1 Function table
Table 3.
Inputs
nOE
L
L
H
H
Function table[1]
nCP
Dn
l
h
l
h
Internal
flip-flops
L
H
L
H
Outputs Q0 to Q7
L
H
Z
Z
[1] H = HIGH voltage level;
L = LOW voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
= LOW-to-HIGH clock transition;
Z = high-impedance OFF-state.
Operating mode
load and read register
load register and disable outputs
74ALVCH16374
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 July 2012
© NXP B.V. 2012. All rights reserved.
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