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74ALVCH162374T 데이터 시트보기 (PDF) - Fairchild Semiconductor

74ALVCH162374T Datasheet PDF : 6 Pages
1 2 3 4 5 6
September 2001
Revised February 2002
Low Voltage 16-Bit D-Type Flip-Flop with Bushold
and 26Series Resistors in Outputs
General Description
The ALVCH162374 contains sixteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP) and output enable (OE) are common to
each byte and can be shorted together for full 16-bit opera-
The ALVCH162374 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The 74ALVCH162374 is also designed with 26series
resistors in the outputs. This design reduces line noise in
applications such as memory address drivers, clock drivers
and bus transceivers/transmitters.
The 74ALVCH162374 is designed for low voltage
(1.65V to 3.6V) VCC applications with output compatibility
up to 3.6V.
The 74ALVCH162374 is fabricated with an advanced
CMOS technology to achieve high speed operation while
maintaining low CMOS power dissipation.
s 1.65V to 3.6V VCC supply operation
s 3.6V tolerant control inputs and outputs
s Bushold data inputs eliminates the need for external
pull-up/pull-down resistors
s 26series resistors in outputs
s tPD (CLK to On)
4.6 ns max for 3.0V to 3.6V VCC
5.4 ns max for 2.3V to 2.7V VCC
9.6 ns max for 1.65V to 1.95V VCC
s Uses patented noise/EMI reduction circuitry
s Latch-up conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model > 200V
Ordering Code:
Order Number
Package Descriptions
MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Output Enable Input (Active LOW)
Clock Pulse Input
Bushold Inputs
© 2002 Fairchild Semiconductor Corporation DS500628

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