Philips Semiconductors
20-bit bus interface D-type latch (3-State)
Product specification
74ALVCH16841
FEATURES
• Wide supply voltage range of 1.2V to 3.6V
• Complies with JEDEC standard no. 8-1A
• Wide supply voltage range of 1.2V to 3.6V
• CMOS low power consumption
• Direct interface with TTL levels
• MULTIBYTETM flow-through standard pin-out architecture
• Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
• Current drive ±24 mA at 3.0 V
• All inputs have bus hold circuitry
• Output drive capability 50Ω transmission lines @ 85°C
• 3-State non-inverting outputs for bus oriented applications
DESCRIPTION
The 74ALVCH16841 has two 10-bit D-type latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. The two sections of each register are controlled
independently by the latch enable (nLE) and output enable (nOE)
control gates.
When nOE is LOW, the data in the registers appears at the outputs.
When nOE is High the outputs are in High-impedance OFF state.
Operation of the nOE input does not affect the state of the flip-flops.
The 74ALVCH16841 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
PIN CONFIGURATION
1OE 1
1Q0 2
1Q1 3
GND 4
1Q2 5
1Q3 6
VCC 7
1Q4 8
1Q5 9
1Q6 10
GND 11
1Q7 12
1Q8 13
1Q9 14
2Q0 15
2Q1 16
2Q2 17
GND 18
2Q3 19
2Q4 20
2Q5 21
VCC 22
2Q6 23
2Q7 24
GND 25
2Q8 26
2Q9 27
2OE 28
56 1LE
55 1D0
54 1D1
53 GND
52 1D2
51 1D3
50 VCC
49 1D4
48 1D5
47 1D6
46 GND
45 1D7
44 1D8
43 1D9
42 2D0
41 2D1
40 2D2
39 GND
38 2D3
37 2D4
36 2D5
35 VCC
34 2D6
33 2D7
32 GND
31 2D8
30 2D9
29 2LE
SA00076
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
tPHL/tPLH
tPHL/tPLH
CI
CPD
Propagation delay
nDn to nQn
Propagation delay
nLE to nQn
Input capacitance
Power dissipation capacitance per buffer
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
VI = GND to VCC1
2.5
2.4
2.5
2.4
5.0
Outputs enabled
19
Outputs disabled
3
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.
UNIT
ns
ns
pF
pF
ORDERING INFORMATION
PACKAGES
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
–40°C to +85°C
74ALVCH16841 DGG
NORTH AMERICA
ACH16841 DGG
DWG NUMBER
SOT364-1
1998 Jul 27
2
853-2093 19785