74ALVCH16374 View Datasheet(PDF) - Philips Electronics

Part Name

Description

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74ALVCH16374

2.5V/3.3V 16-bit edge-triggered D-type flip-flop (3-State)

Philips Electronics 

Philips Semiconductors

16-bit edge-triggered D-type flip-flop (3-State)

Product specification

74ALVCH16374

FEATURES

• Wide supply voltage range of 1.2 V to 3.6 V

• Complies with JEDEC standard no. 8-1A

• CMOS low power consumption

• MULTIBYTETM flow-through standard pin-out architecture

• Low inductance multiple VCC and ground pins for minimum noise

and ground bounce

• Direct interface with TTL levels

• All data inputs have bushold

• Output drive capability 50Ω transmission lines @ 85°C

• Current drive ±24 mA at 3.0 V

DESCRIPTION

The 74ALVCH16374 is a 16-bit edge-triggered flip-flop featuring

separate D-type inputs for each flip-flop and 3-State outputs for bus

oriented applications. Incorporates bus hold data inputs which

eliminate the need for external pull-up or pull-down resistors to hold

unused inputs. The 74ALVCH16374 consists of 2 sections of eight

edge-triggered flip-flops. A clock (CP) input and an output enable

(OE) are provided per 8-bit section.

The flip-flops will store the state of their individual D-inputs that meet

the set-up and hold time requirements on the LOW-to-HIGH CP

transition.

When OE is LOW, the contents of the flip-flops are available at the

outputs. When OE is HIGH, the outputs go to the high impedance

OFF-state. Operation of the OE input does not affect the state of the

flip-flops.

PIN CONFIGURATION

1OE 1

1Q0 2

1Q1 3

GND 4

1Q2 5

1Q3 6

VCC 7

1Q4 8

1Q5 9

GND 10

1Q6 11

1Q7 12

2Q0 13

2Q1 14

GND 15

2Q2 16

2Q3 17

VCC 18

2Q4 19

2Q5 20

GND 21

2Q6 22

2Q7 23

2OE 24

48 1CP

47 1D0

46 1D1

45 GND

44 1D2

43 1D3

42 VCC

41 1D4

40 1D5

39 GND

38 1D6

37 1D7

36 2D0

35 2D1

34 GND

33 2D2

32 2D3

31 VCC

30 2D4

29 2D5

28 GND

27 2D6

26 2D7

25 2CP

QUICK REFERENCE DATA

GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5 ns

SYMBOL

PARAMETER

CONDITIONS

SW00074

TYPICAL

tPHL/tPLH

Propagation delay

CP to Qn

VCC = 2.5V, CL = 30pF

VCC = 3.3V, CL = 50pF

2.3

2.4

fMAX

Maximum clock frequency

VCC = 2.5V

VCC = 3.3V

300

350

CI

Input capacitance

5.0

CPD

Power dissipation capacitance per flip-flop VI = GND to VCC1

Outputs enabled

16

Outputs disabled

10

NOTE:

1. CPD is used to determine the dynamic power dissipation (PD in mW):

PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;

fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.

UNIT

ns

MHz

MHz

pF

pF

ORDERING INFORMATION

PACKAGES

48-Pin Plastic SSOP Type III

48-Pin Plastic TSSOP Type II

TEMPERATURE RANGE OUTSIDE NORTH AMERICA

–40°C to +85°C

74ALVCH16374 DL

–40°C to +85°C

74ALVCH16374 DGG

NORTH AMERICA

ACH16374 DL

ACH16374 DGG

DWG NUMBER

SOT370-1

SOT362-1

1998 Jun 18

2

853-2073 19604

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