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74ACQ573PC View Datasheet(PDF) - Fairchild Semiconductor

Part NameDescriptionManufacturer
74ACQ573PC Quiet Series™ Octal Latch with 3-STATE Outputs Fairchild
Fairchild Semiconductor Fairchild
74ACQ573PC Datasheet PDF : 13 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Logic Symbol
IEEE/IEC
Logic Diagram
Functional Description
The ACQ/ACTQ573 contains eight D-type latches with
3-STATE output buffers. When the Latch Enable (LE)
input is HIGH, data on the Dn inputs enters the latches.
In this condition the latches are transparent, i.e., a latch
output will change state each time its D-type input
changes. When LE is LOW the latches store the informa-
tion that was present on the D-type inputs at setup time
preceding the HIGH-to-LOW transition of LE. The
3-STATE buffers are controlled by the Output Enable
(OE) input. When OE is LOW, the buffers are enabled.
When OE is HIGH the buffers are in the high impedance
mode but this does not interfere with entering new data
into the latches.
Truth Table
Inputs
OE
LE
D
L
H
H
L
H
L
L
L
X
H
X
X
Outputs
On
H
L
O0
Z
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH-to-LOW transition of
Latch Enable
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1990 Fairchild Semiconductor Corporation
74ACQ573, 74ACTQ573 Rev. 1.5
2
www.fairchildsemi.com
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