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74ACT373SJX View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
View to exact match
74ACT373SJX
Fairchild
Fairchild Semiconductor Fairchild
74ACT373SJX Datasheet PDF : 14 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Description
Pin Names
D0–D7
LE
OE
O0–O7
Description
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
Functional Description
The AC/ACT373 contains eight D-type latches with
3-STATE standard outputs. When the Latch Enable (LE)
input is HIGH, data on the Dn inputs enters the latches.
In this condition the latches are transparent, i.e., a latch
output will change state each time its D-type input
changes. When LE is LOW, the latches store the infor-
mation that was present on the D-type inputs a setup
time preceding the HIGH-to-LOW transition of LE. The
3-STATE standard outputs are controlled by the Output
Enable (OE) input. When OE is LOW, the standard
outputs are in the 2-state mode. When OE is HIGH, the
standard outputs are in the high impedance mode but
this does not interfere with entering new data into the
latches.
Truth Table
Inputs
Outputs
LE
OE
Dn
On
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O0
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH-to-LOW transition
of Latch Enable
©1988 Fairchild Semiconductor Corporation
74AC373, 74ACT373 Rev. 1.5.0
2
www.fairchildsemi.com
 

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