16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS235A – MARCH 1990 – REVISED APRIL 1996
D Members of the Texas Instruments
D 3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
D Flow-Through Architecture Optimizes PCB
D Distributed VCC and GND Configuration
Minimizes High-Speed Switching Noise
D EPIC t (Enhanced-Performance Implanted
CMOS) 1-mm Process
D 500-mA Typical Latch-Up Immunity at 125°C
D Package Options Include Plastic Thin
Shrink Small-Outline (DGG) Package,
300-mil Shrink Small-Outline (DL) Package
Using 25-mil Center-to-Center Pin Spacings
and 380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center Pin
The ’AC16245 are 16-bit bus transceivers
organized as dual-octal noninverting 3-state
transceivers designed for asynchronous two-way
communication between data buses. The control
function implementation minimizes external tim-
These devices allow data transmission from the A
bus to the B bus or from the B bus to the A bus,
depending upon the logic level at the direction
control (DIR) input. The output-enable input (OE)
can be used to disable the devices so that the
buses are effectively isolated.
54AC16245 . . . WD PACKAGE
74AC16245 . . . DGG OR DL PACKAGE
The 74AC16245 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54AC16245 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74AC16245 is characterized for operation from –40°C to 85°C.
B data to A bus
A data to bus
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EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
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Production processing does not necessarily include testing of all
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Copyright © 1996, Texas Instruments Incorporated