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74ACT138PC(2000) View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
View to exact match
74ACT138PC
(Rev.:2000)
Fairchild
Fairchild Semiconductor Fairchild
74ACT138PC Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
Truth Table
Inputs
Outputs
E1 E2 E3 A0 A1 A2 O0 O1 O2 O3 O4 O5 O6 O7
HX X X X X HHHHHHHH
X HX X X X HHHHHHHH
XX L XXXHHHHHHHH
L
L
H
L
L
L
L
HH
H
H
H
H
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
L
L
H
L
H
L
HH
L
H
H
H
H
H
L
L
H
H
H
L
HHH
L
H
H
H
H
L
L
H
L
L
H
HHH
H
L
H
H
H
L
L
H
H
L
H
HHH
H
H
L
H
H
L
L
H
L
H
H
HHH
H
H
H
L
H
L
L
H
H
H
H
HHH
H
H
H
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Functional Description
The AC/ACT138 high-speed 1-of-8 decoder/demultiplexer
accepts three binary weighted inputs (A0, A1, A2) and,
when enabled, provides eight mutually exclusive active-
LOW outputs (O0–O7). The AC/ACT138 features three
Enable inputs, two active-LOW (E1, E2) and one active-
HIGH (E3). All outputs will be HIGH unless E1 and E2 are
LOW and E3 is HIGH. This multiple enable function allows
easy parallel expansion of the device to a 1-of-32 (5 lines
to 32 lines) decoder with just four AC/ACT138 devices and
one inverter (see Figure 1). The AC/ACT138 can be used
as an 8-output demultiplexer by using one of the active
LOW Enable inputs as the data input and the other Enable
inputs as strobes. The Enable inputs which are not used
must be permanently tied to their appropriate active-HIGH
or active-LOW state.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
FIGURE 1. Expansion to 1-of-32 Decoding
2
 

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