M74HC112M1R View Datasheet(PDF) - STMicroelectronics

Part Name

Description

View to exact match

M74HC112M1R

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

STMicroelectronics 

M54HC112

M74HC112

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

. HIGH SPEED

fMAX = 67 MHz (TYP.) AT VCC = 5 V

. LOW POWER DISSIPATION

ICC = 2 µA AT TA = 25 °C

. HIGH NOISE IMMUNITY

VNIH = VNIL = 28 % VCC (MIN.)

. OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

. SYMMETRICAL OUTPUT IMPEDANCE

|IOH| = IOL = 4 mA (MIN.)

. BALANCED PROPAGATION DELAYS

tPLH = tPHL

. WIDE OPERATING VOLTAGE RANGE

VCC (OPR) = 2 V TO 6 V

. PIN AND FUNCTION COMPATIBLE

WITH 54/74LS112

DESCRIPTION

B1R

(Plastic Package)

F1R

(Ceramic Package)

M 1R

(Micro Package)

C1R

(Chip Carrier)

ORDER CODES :

M 54HC 11 2F 1R

M 74H C1 12 M1 R

M 74HC 11 2B 1R

M 74H C1 12 C1 R

The M54/74HC112 is a high speed CMOS DUAL J-K

FLIP-FLOP WITH PRESET AND CLEAR fabricated in

silicon gate C2MOS technology. It has the same high

speed performance of LSTTL combined with true

CMOS low power consumption. The

M54HC112/M74HC112 dual JK flip-flop features indi-

vidual J,K, clock, and asynchronous set and clearinputs

for each flip-flop. When the clock goes high, the inputs

are enabled and data will be accepted. The logic level

of the J and K inputs may be allowed to change when

the clock pulse is high and the bistable will function as

shown in the truth table. Input data is transferred to the

input on the negative going edge of the clock pulse. All

inputs are equipped withprotection circuits against static

discharge and transient excess voltage.

PIN CONNECTIONS (top view)

INPUT AND OUTPUT EQUIVALENT CIRCUIT

October 1992

NC =

No Internal

Connection

1/11

Share Link: