56F802X View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

View to exact match

56F802X

16-bit Digital Signal Controllers

Freescale Semiconductor 

56F8025 Signal Pins

Table 2-3 56F8025 Signal and Package Information for the 44-Pin LQFP (Continued)

Signal LQFP

Name Pin No.

Type

State During

Reset

Signal Description

TDO

44

(GPIOD1)

TCK

19

(GPIOD2)

TMS

43

(GPIOD3)

Output

Input/

Output

Input

Input/

Output

Input

Input/

Output

Output

tri-stated,

internal

pull-up

enabled

Test Data Output — This tri-stateable output pin provides a serial

output data stream from the JTAG/EOnCE port. It is driven in the

shift-IR and shift-DR controller states, and changes on the falling

edge of TCK.

Port D GPIO — This GPIO pin can be individually programmed as

an input or output pin.

After reset, the default state is TDO.

Input,

internal

pull-up

enabled

Test Clock Input — This input pin provides a gated clock to

synchronize the test logic and shift serial data to the JTAG/EOnCE

port. The pin is connected internally to a pull-up resistor. A Schmitt

trigger input is used for noise immunity.

Port D GPIO — This GPIO pin can be individually programmed as

an input or output pin.

After reset, the default state is TCK.

Input,

internal

pull-up

enabled

Test Mode Select Input — This input pin is used to sequence the

JTAG TAP controller’s state machine. It is sampled on the rising

edge of TCK and has an on-chip pull-up resistor.

Port D GPIO — This GPIO pin can be individually programmed as

an input or output pin.

After reset, the default state is TMS.

Note: Always tie the TMS pin to VDD through a 2.2K resistor.

Return to Table 2-2

56F8025 Data Sheet, Rev. 3

Freescale Semiconductor

31

Preliminary

Share Link: