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54LS160ALMQB View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
54LS160ALMQB Synchronous Presettable BCD Decade Counters National-Semiconductor
National ->Texas Instruments National-Semiconductor
54LS160ALMQB Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) (Continued)
Symbol
Parameter
Conditions
Min
II
IIH
IIL
IOS
ICCH
ICCL
Input Current Max
Input Voltage
High Level Input Current
Low Level Input Current
Short Circuit
Output Current
Supply Current with
Outputs HIGH
Supply Current with
Outputs LOW
VCC e Max VI e 7V
Other
PE CET Inputs
VCC e Max VI e 2 7V
Other
PE CET Inputs
VCC e Max VI e 0 4V Inputs
54LS
DM74
PE CET Inputs
VCC e Max
(Note 2)
54LS
DM74
VCC e Max PE e GND
CP e L Other Inputs e 4 5V
VCC e Max VIN e GND
CP e L
b20
b20
Typ
(Note 1)
Max
01
02
20
40
b0 4
b1 6
b0 8
b100
b100
31
31
Units
mA
mA
mA
mA
mA
mA
mA
Switching Characteristics VCC e a5 0V TA e a25 C
Symbol
Parameter
RL e 2 kX
CL e 15 pF
Min
Max
fmax
Maximum Clock Frequency
25
tPLH
Propagation Delay
25
tPHL
CP to TC
21
tPLH
Propagation Delay
24
tPHL
CP to Qn
27
tPLH
Propagation Delay
14
tPHL
CET to TC
23
tPHL
Propagation Delay
28
MR to Qn (’160)
Units
MHz
ns
ns
ns
ns
Functional Description
The ’LS160 and ’LS162 count modulo-10 in the BCD (8421)
sequence From state 9 (HLLH) they increment to state 0
(LLLL) The ’161 and ’163 count modulo-16 binary se-
quence From state 15 (HHHH) they increment to state 0
(LLLL) The clock inputs of all flip-flops are driven in parallel
through a clock buffer Thus all changes of the Q outputs
(except due to Master Reset of the ’LS160) occur as a re-
sult of and synchronous with the LOW-to-HIGH transition
of the CP input signal The circuits have four fundamental
modes of operation in order of precedence asynchronous
reset (’LS160) synchronous reset (’LS162) parallel load
count-up and hold Five control inputs Master Reset (MR
’LS160) Synchronous Reset (SR ’LS162) Parallel Enable
(PE) Count Enable Parallel (CEP) and Count Enable Trickle
(CET) determine the mode of operation as shown in the
Mode Select Table A LOW signal on MR overrides all other
inputs and asynchronously forces all outputs LOW A LOW
signal on SR overrides counting and parallel loading and
allows all outputs to go LOW on the next rising edge of CP
A LOW signal on PE overrides counting and allows informa-
tion on the Parallel Data (Pn) inputs to be loaded into the
flip-flops on the next rising edge of CP With PE and MR
(’LS160) or SR (’LS162) HIGH CEP and CET permit count-
ing when both are HIGH Conversely a LOW signal on ei-
ther CEP or CET inhibits counting
The ’LS160A and ’LS162A use D-type edge-triggered flip-
flops and changing the SR PE CEP and CET inputs when
the CP is in either state does not cause errors provided that
the recommended setup and hold times with respect to the
rising edge of CP are observed
3
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