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54ACT257F View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
54ACT257F Quad 2-Input Multiplexer with TRI-STATE® Outputs National-Semiconductor
National ->Texas Instruments National-Semiconductor
54ACT257F Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
Connection Diagrams
Pin Assignment for
DIP and Flatpak
DS100286-3
Pin Assignment for LCC
DS100286-4
Logic Diagram
Functional Description
The ’AC/’ACT257 is quad 2-input multiplexer with
TRI-STATE outputs. It selects four bits of data from two
sources under control of a Common Data Select input. When
the Select input is LOW, the I0x inputs are selected and when
Select is HIGH, the I1x inputs are selected. The data on the
selected inputs appears at the outputs in true (noninverted)
form. The device is the logic implementation of a 4-pole,
2-position switch where the position of the switch is deter-
mined by the logic levels supplied to the Select input. The
logic equations for the outputs are shown below:
Za = OE (11a S + I0a S)
Zb = OE (11b S + I0b S)
Zc = OE (11c S + I0c S)
Zd = OE (11d S + I0d S)
When the Output Enable (OE) is HIGH, the outputs are
forced to a high impedance state. If the outputs are tied to-
gether, all but one device must be in the high impedance
state to avoid high currents that would exceed the maximum
ratings. Designers should ensure the Output Enable signals
to TRI-STATE devices whose outputs are tied together are
designed so there is no overlap.
Truth Table
Output
Select
Enable
Input
OE
S
H
X
L
H
L
H
L
L
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Data
Inputs
I0
I1
X
X
X
L
X
H
L
X
H
X
Outputs
Z
Z
L
H
L
H
DS100286-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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