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54ACT175D View Datasheet(PDF) - National ->Texas Instruments

Part Name54ACT175D National-Semiconductor
National ->Texas Instruments National-Semiconductor
DescriptionQuad D Flip-Flop
54ACT175D Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
AC Electrical Characteristics
Symbol
Parameter
fmax
Maximum Clock
Frequency
tPLH
Propagation Delay
CP to Qn or Qn
tPHL
Propagation Delay
CP to Qn or Qn
tPLH
Propagation Delay
MR to Qn
tPHL
Propagation Delay
MR to Qn
Note 10: Voltage Range 5.0 is 5.0V ±0.5V
VCC
(V)
(Note 10)
5.0
5.0
5.0
5.0
5.0
AC Operating Requirements
Symbol
Parameter
ts (H)
ts (L)
th
tw
Setup Time
Dn to CP
Hold Time, HIGH or LOW
Dn to CP
CP Pulse Width
HIGH or LOW
tw
MR Pulse Width, LOW
trec
Recovery Time, MR to CP
Note 11: Voltage Range 5.0 is 5.0V ±0.5V
VCC
(V)
(Note 11)
5.0
5.0
5.0
5.0
5.0
Capacitance
Symbol
Parameter
Typ
CIN
Input Capacitance
4.5
CPD
Power Dissipation
45.0
Capacitance
54ACT
TA = −55˚C to +125˚C
CL = 50 pF
Min
Max
95
1.5
11.5
1.5
12.5
1.5
11.5
1.5
11.0
Units
MHz
ns
ns
ns
ns
54ACT
TA = −55˚C to +125˚C
CL = 50 pF
Guaranteed Minimum
3.5
3.5
1.5
5.0
5.0
1.5
Units
ns
ns
ns
ns
ns
Units
pF
pF
Conditions
VCC = OPEN
VCC = 5.0V
Fig.
No.
Fig.
No.
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6
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General Description
The ’AC/’ACT175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D in puts is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when LOW.

Features
■ Edge-triggered D-type inputs
■ Buffered positive edge-triggered clock
■ Asynchronous common reset
■ True and complement output
■ Outputs source/sink 24 mA
■ ’ACT175 has TTL-compatible inputs
■ Standard Microcircuit Drawing (SMD)
   — ’AC175: 5962-89552
   — ’ACT175: 5962-89693

 

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