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54ACT175D View Datasheet(PDF) - National ->Texas Instruments

Part Name54ACT175D National-Semiconductor
National ->Texas Instruments National-Semiconductor
DescriptionQuad D Flip-Flop
54ACT175D Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
DC Characteristics for ’AC Family Devices (Continued)
Symbol
Parameter
ICC
Maximum Quiescent
Supply Current
54AC
VCC
TA = −55˚C to +125˚C
(V)
Guaranteed Limits
5.5
160.0
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C.
DC Characteristics for ’ACT Family Devices
Symbol
Parameter
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
VOH
Minimum High Level
Output Voltage
54ACT
VCC
TA = −55˚C to +125˚C
(V)
Guaranteed Limits
4.5
2.0
5.5
2.0
4.5
0.8
5.5
0.8
4.5
4.4
5.5
5.4
4.5
3.70
5.5
4.70
VOL
Maximum Low Level
4.5
0.1
Output Voltage
5.5
0.1
4.5
5.5
IIN
Maximum Input
5.5
Leakage Current
ICCT
Maximum
5.5
ICC/Input
(Note 6)
IOLD
Minimum Dynamic
5.5
IOHD
Output Current
5.5
ICC
Maximum Quiescent
5.5
Supply Current
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
Note 7: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C.
0.50
0.50
±1.0
1.6
50
−50
160.0
Units
Conditions
µA
VIN = VCC
or GND
Units
Conditions
V
VOUT = 0.1V
or VCC − 0.1V
V
VOUT = 0.1V
or VCC − 0.1V
V
IOUT = −50 µA
(Note 5)
VIN = VIL or VIH
V
IOH = −24 mA
IOH = −24 mA
V
IOUT = 50 µA
(Note 5)
VIN = VIL or VIH
V
IOL = 24 mA
IOL = 24 mA
µA
VI = VCC, GND
mA
VI = VCC − 2.1V
mA
VOLD = 1.65V Max
mA
VOHD = 3.85V Min
µA
VIN = VCC
or GND
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General Description
The ’AC/’ACT175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D in puts is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when LOW.

Features
■ Edge-triggered D-type inputs
■ Buffered positive edge-triggered clock
■ Asynchronous common reset
■ True and complement output
■ Outputs source/sink 24 mA
■ ’ACT175 has TTL-compatible inputs
■ Standard Microcircuit Drawing (SMD)
   — ’AC175: 5962-89552
   — ’ACT175: 5962-89693

 

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