The ’AC/’ACT175 consists of four edge-triggered D flip-flops
with individual D inputs and Q and Q outputs. The Clock and
Master Reset are common. The four flip-flops will store the
state of their individual D inputs on the LOW-to-HIGH clock
(CP) transition, causing individual Q and Q outputs to follow.
A LOW input on the Master Reset (MR) will force all Q out-
puts LOW and Q outputs HIGH independent of Clock or Data
inputs. The ’AC/’ACT175 is useful for general logic applica-
tions where a common Master Reset and Clock are
@ tn, MR = H
H = HIGH Voltage Level
L = LOW Voltage Level
tn = Bit Time before Clock Pulse
tn+1 = Bit Time after Clock Pulse
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.