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54ACT163D View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
54ACT163D Synchronous Presettable Binary Counter National-Semiconductor
National ->Texas Instruments National-Semiconductor
54ACT163D Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Connection Diagrams
Pin Assignment
for DIP and Flatpak
Pin Assignment
for LCC
Functional Description
The ’AC/’ACT163 counts in modulo-16 binary sequence.
From state 15 (HHHH) it increments to state 0 (LLLL). The
clock inputs of all flip-flops are driven in parallel through a
clock buffer. Thus all changes of the Q outputs occur as a re-
sult of, and synchronous with, the LOW-to-HIGH transition of
the CP input signal. The circuits have four fundamental
modes of operation, in order of precedence: synchronous re-
set, parallel load, count-up and hold. Four control
inputs — Synchronous Reset (SR), Parallel Enable (PE),
Count Enable Parallel (CEP) and Count Enable Trickle
(CET) — determine the mode of operation, as shown in the
Mode Select Table. A LOW signal on SR overrides counting
and parallel loading and allows all outputs to go LOW on the
next rising edge of CP. A LOW signal on PE overrides count-
ing and allows information on the Parallel Data (Pn) inputs to
be loaded into the flip-flops on the next rising edge of CP.
With PE and SR HIGH, CEP and CET permit counting when
both are HIGH. Conversely, a LOW signal on either CEP or
CET inhibits counting.
The ’AC/’ACT163 uses D-type edge-triggered flip-flops and
changing the SR, PE, CEP and CET inputs when the CP is
in either state does not cause errors, provided that the rec-
ommended setup and hold times, with respect to the rising
edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is HIGH
and counter is in state 15. To implement synchronous multi-
stage counters, the TC outputs can be used with the CEP
and CET inputs in two different ways.
Figure 1 shows the connections for simple ripple carry, in
which the clock period must be longer than the CP to TC de-
lay of the first stage, plus the cumulative CET to TC delays of
the intermediate stages, plus the CET to CP setup time of
the last stage. This total delay plus setup time sets the upper
limit on clock frequency. For faster clock rates, the carry loo-
kahead connections shown in Figure 2 are recommended. In
this scheme the ripple delay through the intermediate stages
commences with the same clock that causes the first stage
to tick over from max to min in the Up mode, or min to max
in the Down mode, to start its final cycle. Since this final
cycle takes 16 clocks to complete, there is plenty of time for
the ripple to progress through the intermediate stages. The
critical timing that limits the clock period is the CP to TC de-
lay of the first stage plus the CEP to CP setup time of the last
stage. The TC output is subject to decoding spikes due to in-
ternal race conditions and is therefore not recommended for
use as a clock or asynchronous reset for flip-flops, registers
or counters.
Logic Equations: Count Enable = CEP CET PE
TC = Q0 Q1 Q2 Q3 CET
Mode Select Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Action on the Rising
Clock Edge (N)
Reset (Clear)
Load (Pn Qn)
Count (Increment)
No Change (Hold)
No Change (Hold)
State Diagram
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