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54ACT161L View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
54ACT161L Synchronous Presettable Binary Counter National-Semiconductor
National ->Texas Instruments National-Semiconductor
54ACT161L Datasheet PDF : 13 Pages
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Connection Diagrams
Pin Assignment
for DIP and Flatpak
DS100274-3
Pin Assignment
for LCC
DS100274-4
Functional Description
The ’AC/’ACT161 count in modulo-16 binary sequence.
From state 15 (HHHH) they increment to state 0 (LLLL). The
clock inputs of all flip-flops are driven in parallel through a
clock buffer. Thus all changes of the Q outputs (except due
to Master Reset of the ’161) occur as a result of, and syn-
chronous with, the LOW-to-HIGH transition of the CP input
signal. The circuits have four fundamental modes of opera-
tion, in order of precedence: asynchronous reset, parallel
load, count-up and hold. Five control inputs — Master Reset,
Parallel Enable (PE), Count Enable Parallel (CEP) and
Count Enable Trickle (CET) — determine the mode of opera-
tion, as shown in the Mode Select Table. A LOW signal on
MR overrides all other inputs and asynchronously forces all
outputs LOW. A LOW signal on PE overrides counting and
allows information on the Parallel Data (Pn) inputs to be
loaded into the flip-flops on the next rising edge of CP. With
PE and MR HIGH, CEP and CET permit counting when both
are HIGH. Conversely, a LOW signal on either CEP or CET
inhibits counting.
The ’AC/’ACT161 use D-type edge-triggered flip-flops and
changing the PE, CEP and CET inputs when the CP is in ei-
ther state does not cause errors, provided that the recom-
mended setup and hold times, with respect to the rising edge
of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is HIGH
and counter is in state 15. To implement synchronous multi-
stage counters, the TC outputs can be used with the CEP
and CET inputs in two different ways.
Figure 1 shows the connections for simple ripple carry, in
which the clock period must be longer than the CP to TC de-
lay of the first stage, plus the cumulative CET to TC delays of
the intermediate stages, plus the CET to CP setup time of
the last stage. This total delay plus setup time sets the upper
limit on clock frequency. For faster clock rates, the carry loo-
kahead connections shown in Figure 2 are recommended. In
this scheme the ripple delay through the intermediate stages
commences with the same clock that causes the first stage
to tick over from max to min in the Up mode, or min to max
in the Down mode, to start its final cycle. Since this final
cycle requires 16 clocks to complete, there is plenty of time
for the ripple to progress through the intermediate stages.
The critical timing that limits the clock period is the CP to TC
delay of the first stage plus the CEP to CP setup time of the
last stage. The TC output is subject to decoding spikes due
to internal race conditions and is therefore not recom-
mended for use as a clock or asynchronous reset for
flip-flops, registers or counters.
Logic Equations: Count Enable = CEP CET PE
TC = Q0 Q1 Q2 Q3 CET
Mode Select Table
PE
CET
CEP
X
X
X
L
X
X
H
H
H
H
L
X
H
X
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Action on the Rising
Clock Edge (N)
Reset (Clear)
Load (PnQn)
Count (Increment)
No Change (Hold)
No Change (Hold)
State Diagram
DS100274-5
www.national.com
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