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54ACT109L View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
54ACT109L Dual JK Positive Edge-Triggered Flip-Flop National-Semiconductor
National ->Texas Instruments National-Semiconductor
54ACT109L Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
August 1998
54AC109 54ACT109
Dual JK Positive Edge-Triggered Flip-Flop
General Description
The ’AC/’ACT109 consists of two high-speed completely in-
dependent transition clocked JK flip-flops. The clocking op-
eration is independent of rise and fall times of the clock
waveform. The JK design allows operation as a D flip-flop
(refer to ’AC/’ACT74 data sheet) by connecting the J and K
inputs together.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q
n ICC reduced by 50%
n Outputs source/sink 24 mA
n ’ACT109 has TTL-compatible inputs
n Standard Military Drawing (SMD)
— ’AC109: 5962-89551
— ’ACT109: 5962-88534
Logic Symbol
Pin Names
J1, J2, K1, K2
CP1, CP2
CD1, CD2
SD1, SD2
Q1, Q2, Q1, Q2
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100267
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