datasheetbank_Logo   Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site
Part Name :   

N14A View Datasheet(PDF) - Fairchild Semiconductor

Part NameDescriptionManufacturer
N14A Quad Bilateral Switch Fairchild
Fairchild Semiconductor Fairchild
N14A Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
AC Electrical Characteristics (Note 3)
TA = 25°C, tr = tf = 20 ns and VSS = 0V unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tPHL, tPLH
Propagation Delay Time Signal
Input to Signal Output
tPZH, tPZL
tPHZ, tPLZ
Propagation Delay Time
Control Input to Signal
Output High Impedance to
Logical Level
Propagation Delay Time
Control Input to Signal
Output Logical Level to
High Impedance
Sine Wave Distortion
Frequency Response-Switch
ON(Frequency at 3 dB)
VC = VDD, CL = 50 pF, (Figure 1)
RL = 200k
VDD = 5V
VDD = 10V
VDD = 15V
RL = 1.0 k, CL = 50 pF, (Figure 2, Figure 3)
VDD = 5V
VDD = 10V
VDD = 15V
RL = 1.0 k, CL = 50 pF, (Figure 2, Figure 3)
VDD = 5V
VDD = 10V
VDD = 15V
VC = VDD = 5V, VSS = −5V
RL = 10 k, VIS = 5Vp-p, f= 1 kHz, (Figure 4)
VC = VDD = 5V, VSS = −5V,
RL = 1 k, VIS = 5Vp-p,
20 Log10 VOS/VOS (1 kHz)dB,
(Figure 4)
25
55
ns
15
35
ns
10
25
ns
125
ns
60
ns
50
ns
125
ns
60
ns
50
ns
0.1
%
40
MHz
Feedthrough Switch OFF
(Frequency at 50 dB)
Crosstalk Between Any Two
Switches (Frequency at 50 dB)
Crosstalk; Control Input to
Signal Output
VDD = 5.0V, VCC = VSS = −5.0V,
RL = 1 k, VIS = 5.0Vp-p, 20 Log10,
VOS/VIS = −50 dB, (Figure 4)
VDD = VC(A) = 5.0V; VSS = VC(B) = 5.0V,
RL1 k, VIS(A) = 5.0 Vp-p, 20 Log10,
VOS(B)/VIS(A) = −50 dB (Figure 5)
VDD = 10V, RL = 10 k, RIN = 1.0 k,
VCC = 10V Square Wave, CL = 50 pF
(Figure 6)
1.25
0.9
150
MHz
mVp-p
Maximum Control Input
CIS
COS
CIOS
Signal Input Capacitance
Signal Output Capacitance
Feedthrough Capacitance
RL = 1.0 k, CL = 50 pF, (Figure 7)
VOS(f) = ½ VOS(1.0 kHz)
VDD = 5.0V
VDD = 10V
VDD = 15V
VDD = 10V
VC = 0V
6.0
MHz
8.0
MHz
8.5
MHz
8.0
pF
8.0
pF
0.5
pF
CIN
Control Input Capacitance
Note 3: AC Parameters are guaranteed by DC correlated testing.
5.0
7.5
pF
Note 4: These devices should not be connected to circuits with the power ON.
Note 5: In all cases, there is approximately 5 pF of probe and jig capacitance in the output; however, this capacitance is included in CL wherever it is
specified.
Note 6: VIS is the voltage at the in/out pin and VOS is the voltage at the out/in pin. VC is the voltage at the control input.
Note 7: Conditions for VIHC: a) VIS = VDD, IOS = standard B series IOH b) VIS = 0V, IOL = standard B series IOL.
3
www.fairchildsemi.com
Direct download click here
 

Share Link : Fairchild
All Rights Reserved © datasheetbank.com 2014 - 2019 [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]