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M29F100BT45N6 View Datasheet(PDF) - STMicroelectronics

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M29F100BT45N6 Datasheet PDF : 22 Pages
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M29F100BT, M29F100BB
Standby. When Chip Enable is High, VIH, the
Data Inputs/Outputs pins are placed in the high-
impedance state and the Supply Current is re-
duced to the Standby level.
When Chip Enable is at VIH the Supply Current is
reduced to the TTL Standby Supply Current, ICC2.
To further reduce the Supply Current to the CMOS
Standby Supply Current, ICC3, Chip Enable should
be held within VCC ± 0.2V. For Standby current
levels see Table 13, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, ICC4, for Program or Erase operations un-
til the operation completes.
Automatic Standby. If CMOS levels (VCC ± 0.2V)
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the CMOS Standby Supply Current, ICC3.
The Data Inputs/Outputs will still output data if a
Bus Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera-
tions are intended for use by programming equip-
ment and are not usually used in applications.
They require VID to be applied to some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 5 and 6, Bus Operations.
Block Protection and Blocks Unprotection. Each
block can be separately protected against acci-
dental Program or Erase. Protected blocks can be
unprotected to allow data to be changed.
There are two methods available for protecting
and unprotecting the blocks, one for use on pro-
gramming equipment and the other for in-system
use. For further information refer to Application
Note AN1122, Applying Protection and Unprotec-
tion to M29 Series Flash.
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
The address used for the commands changes de-
pending on whether the memory is in 16-bit or 8-
bit mode. See either Table 7, or 8, depending on
the configuration that is being used, for a summary
of the commands.
Read/Reset Command. The Read/Reset com-
mand returns the memory to its Read mode where
it behaves like a ROM or EPROM. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be used to issue
the Read/Reset command.
If the Read/Reset command is issued during a
Block Erase operation or following a Programming
or Erase error then the memory will take upto 10µs
to abort. During the abort period no valid data can
be read from the memory. Issuing a Read/Reset
command during a Block Erase operation will
leave invalid data in the memory.
Auto Select Command. The Auto Select com-
mand is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are re-
quired to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until another com-
mand is issued.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = VIL and A1 = VIL. The other address bits
may be set to either VIL or VIH. The Manufacturer
Code for STMicroelectronics is 0020h.
The Device Code can be read using a Bus Read
operation with A0 = VIH and A1 = VIL. The other
address bits may be set to either VIL or VIH. The
Device Code for the M29F100BT is 00D0h and for
the M29F100BB is 00D1h.
The Block Protection Status of each block can be
read using a Bus Read operation with A0 = VIL,
A1 = VIH, and A12-A15 specifying the address of
the block. The other address bits may be set to ei-
ther VIL or VIH. If the addressed block is protect-
ed then 01h is output on Data Inputs/Outputs
DQ0-DQ7, otherwise 00h is output.
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