datasheetbank_Logo   Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site
Part Name :   

M29F100BB70M1T View Datasheet(PDF) - STMicroelectronics

Part NameDescriptionManufacturer
M29F100BB70M1T 1 Mbit (128Kb x8 or 64Kb x16, Boot Block) Single Supply Flash Memory ST-Microelectronics
STMicroelectronics ST-Microelectronics
M29F100BB70M1T Datasheet PDF : 22 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
M29F100BT, M29F100BB
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Tables 5 and 6, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the
value, see Figure 8, Read Mode AC Waveforms,
and Table 14, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, VIH, during the whole Bus
Write operation. See Figures 9 and 10, Write AC
Waveforms, and Tables 15 and 16, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
Table 5. Bus Operations, BYTE = VIL
Operation
E
G
W
Bus Read
VIL
VIL
VIH
Bus Write
VIL
VIH
VIL
Output Disable
X
VIH
VIH
Standby
VIH
X
X
Read Manufacturer
Code
VIL
VIL
VIH
Read Device Code
VIL
VIL
VIH
Note: X = VIL or VIH.
Address Inputs
DQ15A–1, A0-A15
Data Inputs/Outpu ts
DQ14-DQ8
DQ7-DQ0
Cell Address
Hi-Z
Data Output
Command Address
Hi-Z
Data Input
X
Hi-Z
Hi-Z
X
Hi-Z
Hi-Z
A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH
Hi-Z
20h
A0 = VIH, A1 = VIL, A9 = VID,
Others VIL or VIH
Hi-Z
D0h (M29F100BT)
D1h (M29F100BB)
Table 6. Bus Operations, BYTE = VIH
Operation
E
G
W
Bus Read
VIL
VIL
VIH
Bus Write
VIL
VIH
VIL
Output Disable
X
VIH
VIH
Standby
VIH
X
X
Read Manufacturer
Code
VIL
VIL
VIH
Read Device Code
VIL
VIL
VIH
Note: X = VIL or VIH.
Address Inputs
A0-A15
Cell Address
Command Address
X
X
A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH
A0 = VIH, A1 = VIL, A9 = VID,
Others VIL or VIH
Data Inputs/Outpu ts
DQ15A–1, DQ14-DQ0
Data Output
Data Input
Hi-Z
Hi-Z
0020h
00D0h (M29F100BT)
00D1h (M29F100BB)
5/22
Direct download click here
 

Share Link : ST-Microelectronics
All Rights Reserved © datasheetbank.com 2014 - 2019 [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]