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M29F100BT45N6 View Datasheet(PDF) - STMicroelectronics

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M29F100BT45N6 Datasheet PDF : 22 Pages
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Figure 4. Data Polling Flowchart
START
READ DQ5 & DQ7
at VALID ADDRESS
DQ= 7 YES
DATA
NO
NO DQ5
=1
YES
READ DQ7
at VALID ADDRESS
DQ7
=
YES
DATA
NO
FAIL
PASS
AI03598
M29F100BT, M29F100BB
Figure 5. Data Toggle Flowchart
START
READ
DQ5 & DQ6
READ DQ6
DQ= 6
NO
TOGGLE
YES
NO DQ5
=1
YES
READ DQ6
TWICE
DQ= 6
NO
TOGGLE
YES
FAIL
PASS
AI01370B
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase com-
mand. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional blocks to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Al-
ternative Toggle Bit is output on DQ2 when the
Status Register is read.
During Chip Erase and Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations from addresses
within the blocks being erased. Once the operation
completes the memory returns to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to ad-
dresses within blocks not being erased will output
the memory cell data as if in Read mode.
After an Erase operation that causes the Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the er-
ror. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Opera-
tions from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change if the addressed block has erased cor-
rectly.
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