M68AF127B
Figure 14. E1 Controlled, Low VCC Data Retention AC Waveforms
5.5V
VCC
4.5V
VDR > 2.0V
E1
DATA RETENTION MODE
tCDR
E1 ≥ VDR – 0.2V
Figure 15. E2 Controlled, Low VCC Data Retention AC Waveforms
5.5V
VCC
4.5V
VDR > 2.0V
E2
DATA RETENTION MODE
tCDR
E2 ≤ 0.2V
tR
AI07204
tR
AI07205B
Table 9. Low VCC Data Retention Characteristics
Symbol
Parameter
Test Condition
Min
ICCDR (1) Supply Current (Data Retention)
VCC = 2.0V, E1 ≥ VCC –0.2V or
E2 ≤0.2V, f = 0
tCDR (1,2) Chip Deselected to Data Retention Time
0
tR (2) Operation Recovery Time
tAVAV
VDR (1) Supply Voltage (Data Retention)
E1 ≥ VCC –0.2V or E2 ≤0.2V, f = 0 2.0
Note: 1. All other Inputs at VIH ≥ VCC –0.2V or VIL ≤0.2V.
2. Tested initially and after any design or process that may affect these parameters. tAVAV is Read cycle time.
3. No input may exceed VCC +0.2V.
Max
4.5
Unit
µA
ns
ns
V
16/23