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J222 View Datasheet(PDF) - Renesas Electronics

Part NameDescriptionManufacturer
J222 Silicon P-Channel MOS FET Renesas
Renesas Electronics Renesas
J222 Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
2SJ222
Reverse Drain Current vs.
Source to Drain Voltage
–50
Pulse Test
–40
–30
–20
10 V
5 V
–10
VGS = 0, 5 V
0
0 –0.4 –0.8 –1.2 –1.6 –2.0
Source to Drain Voltage VSD (V)
Normalized Transient Thermal Impedance vs. Pulse Width
3
D=1
1
0.5
Tc = 25°C
0.3
0.2
0.1
0.1
0.05
0.03 0.02
0.01
10 µ
0.01
1shot
pulse
100 µ
θch – c (t) = γ s (t) • θch – c
θch – c = 3.57°C/W, Tc = 25°C
PDM
D=
PW
T
PW
T
1m
10 m
100 m
1
10
Pulse Width PW (S)
Switching Time Test Circuit
Vin Monitor
D.U.T.
Vout
Monitor
RL
Vin
–10 V
50
VDD
= –30 V
Waveform
Vin
10%
90%
90%
90%
Vout
td(on)
10%
tr
td(off)
10%
tf
Rev.2.00 Sep 07, 2005 page 5 of 6
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